http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6479847-B2

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
filingDate 1999-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2002-11-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3792241888fb2ce99c9a7eb93a7bc61f
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publicationDate 2002-11-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6479847-B2
titleOfInvention Method for complementary oxide transistor fabrication
abstract A method of manufacturing an integrated circuit device includes forming a laminated structure having a first side and a second side, the first side includes a first type Mott channel layer and the second side includes a second type Mott channel layer. A first source region and a first drain region is formed on the first side, a second source region and a second drain region is formed on the second side, a first gate region is formed on the second side, opposite the first source region and the first drain region and a second gate region is formed on the first side, opposite the second source region and the second drain region. The first source, the first drain and the first gate comprise a first type field effect transistor and the second source, the second drain and the second gate comprise a second type field effect transistor.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016043142-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7163864-B1
priorityDate 1999-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 28.