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filingDate 1996-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2002-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6429473-B1
titleOfInvention DRAM cell with stacked capacitor self-aligned to bitline
abstract A semiconductor chip with uniform topology includes a memory cell having a stacked capacitor self-aligned with a bitline. Thick insulation on the bitline and on interconnect wiring on supports circuits of the chip serves to provide the uniform topology and to provide for the self-alignment of the capacitor and bitline. Bitlines and support circuit interconnect wiring are both formed from the same level of metal but they are patterned in separate masking steps. The stacked capacitors are separated from each other by less than the minimum dimension of the photolithographic system used for fabrication.
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