| abstract |
A delay locked loop circuit prevents occurrence of jitter and has a small chip area when it is realized as a semiconductor integrated circuit. The delay locked loop circuit includes a phase shifter, a compensation delay unit, a component coefficient extractor, a phase inverter, first and second component signal generators, and a phase mixer. In this structure, the delay locked loop circuit generates an output clock signal, the phase of which leads that of an externally-applied input clock signal by a predetermined delay time to compensate for a delay time which inevitably occurs in semiconductor integrated circuits. The phase shifter generates a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal. The compensation delay unit outputs a third clock signal, the phase of which lags that of the input clock signal by a predetermined delay time. The component coefficient extractor extracts first and second component coefficients of the third clock signal. The phase inverter inverts the phase of the second component coefficient. The first component signal generator generates a first component signal by multiplying the first component coefficient by the first clock signal. The second component signal generator generates a second component signal by multiplying the inverted second component coefficient by the second clock signal. The phase mixer mixes the first and second component signals to generate the output clock signal. |