| abstract |
A conductive layer ( 14 ) and a dummy feature ( 16 ) are formed over a semiconductor substrate ( 10 ) doped with a first dopant type. A spacer ( 42 ) is then formed adjacent the dummy feature ( 16 ) and is used to define a first patterned feature ( 92 ). In one embodiment, substrate regions ( 90 ) are doped with a second dopant type that is a same dopant type as the first dopant type. In an alternative embodiment, substrate regions ( 90 ) are doped with a second dopant type that is opposite the first dopant type. The dummy feature ( 16 ) is then removed and remaining portions of the spacer ( 100 ) are used to define a gate electrode ( 120 ). The substrate ( 10 ) is then doped optionally with a third dopant type and then with a fourth dopant type, the third and fourth dopant types being opposite the first dopant type, to form asymmetrically doped source ( 172 ) and drain regions ( 174 ) in the semiconductor substrate ( 10 ). |