http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6362023-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a0f26a9c2efad3ae086a108f3c04b57d |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5252 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-525 |
| filingDate | 2001-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2002-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fb65e647cd80fdc2cfe654a9761030a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3b8fe4b1b80cf12a39dd5b31c684afe |
| publicationDate | 2002-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-6362023-B1 |
| titleOfInvention | Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture |
| abstract | A dielectric-based anti-fuse cell and cell array, that include a doped polysilicon contact plug, with a low resistance in the programmed state, a low capacitance, and a small cell area. The dielectric-based anti-fuse cell includes a first insulating layer, typically SiO 2 , on the surface of a semiconductor substrate. A first doped polysilicon (poly 1) layer is on the upper surface of the first insulating layer and a second insulating layer is over the poly 1 layer. A doped polysilicon contact plug extends through the second insulating layer and into the poly 1 layer. A dielectric layer, typically either an ONO or NO dielectric composite layer, covers the upper surface of the doped polysilicon contact plug. A second doped polysilicon (poly 2) layer is disposed on the dielectric layer. n A process for manufacturing the anti-fuse cell and array includes first providing a semiconductor substrate and forming a first insulating layer on its surface. Next a poly 1 layer (e.g. bit lines) is formed on the surface of the first insulating layer followed by the formation of a second insulating layer over the poly 1 layer. A contact opening that extends into the poly 1 layer is then created in the second insulating layer and filled with a doped polysilicon contact plug. Next, a dielectric layer is formed on the upper surface of the doped polysilicon contact plug, followed by the formation of a poly 2 layer (e.g. word lines) on the upper surface of the dielectric layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007222000-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005158986-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7982285-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7015126-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7241674-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7256137-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004067635-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008111210-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008029844-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005253204-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6509209-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6884736-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006011996-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004108573-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003186533-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6515343-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9184129-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7396767-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011101496-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6844259-B2 |
| priorityDate | 1998-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.