| abstract |
A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconnection level. This eliminates the problem of dishing of the relatively large bonding pads which occurs, during chemical mechanical polishing, when the bonding pads are on the same level as the interconnection metallurgy. The interconnection wiring includes a smaller pad base segment upon which the larger bonding pad is then formed. The bonding pad base segments are small enough that dishing during CMP is not a problem. Placing the bonding pads on pad bases provides for a more robust pad. The top level and bonding pad fabrication procedures are applicable with various conductive materials including aluminum, tungsten, and copper. |