| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e13bd2d476d53df53aa23a34d06fa01 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-60 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-55 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate |
2000-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2002-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3c2b08eeec76d75c63f151fdd30600f8 |
| publicationDate |
2002-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6358755-B1 |
| titleOfInvention |
Ferroelectric memory device structure useful for preventing hydrogen line degradation |
| abstract |
A ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and third dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a second via through the first, second, and third dielectric layers to provide access to a second transistor source/drain; forming a third via through the third dielectric layer to provide access to the top electrode; metalizing the first via; metalizing the second via; and metalizing the third via. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6579727-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9595576-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10347829-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9985075-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007170484-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7804706-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8658435-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8395196-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010123207-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9092582-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8552515-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9318693-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8916434-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10741748-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005009209-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9846664-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8518792-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8518791-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8728901-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9502466-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8222683-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8497539-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6906365-B2 |
| priorityDate |
1998-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |