| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28512
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
1999-09-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2002-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42032999c1800d7a5f147217a91b4832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_120eb47d21b34ef9e8b55fad42db900c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39d567af3496d04373ec26885e23a417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c0b07679a04d53842bf2d0075fe9eb12 |
| publicationDate |
2002-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6351016-B1 |
| titleOfInvention |
Technology for high performance buried contact and tungsten polycide gate integration |
| abstract |
A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6613637-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008105928-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005253204-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7241674-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7015126-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006281302-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006134898-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7029963-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003042546-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7564104-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6737342-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007222000-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004067635-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005158986-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7396767-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6884736-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7256137-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9490263-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006011996-A1 |
| priorityDate |
1998-03-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |