http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6331495-B1

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
filingDate 1999-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2001-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_51720eac2e27f60d8c32fa082c024d79
publicationDate 2001-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6331495-B1
titleOfInvention Semiconductor structure useful in a self-aligned contact etch and method for making same
abstract A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.
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priorityDate 1998-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 47.