| abstract |
An SRAM memory cell device is provide having a single transistor and a single RTD latch structure. The single transistor and RTD latch structure are formed on a very thin silicon layer, typically in the range of 250 to 300 Å thick, allowing for increased memory cell density over a given area. The RTD latch structure is a lateral RTD device, such that the outer contacting regions, the tunneling barriers and the central quantum well are formed side-by-side as opposed to being stacked on top of one another. This allows for formation of the memory cell device on very thin silicon layers. The layers can then be stacked to form memory devices for use with computers and the like. The memory device can be formed employing silicon-on-insulator (SOI) technology to take advantage of SOI device characteristics. |