| abstract |
The semiconductor integrated circuit device for reading data synchronously with an external clock signal, comprises: a memory cell array in which memory cells are arranged in a matrix; first and second address specifying devices for alternately specifying continuous internal addresses in the memory cell array starting from an external address synchronously with the external clock signal; first and second data transfer devices, which correspond to the respective first and second address specifying devices, for alternately transferring the data from the memory cells in the memory cell array specified by the internal addresses synchronously with the external clock; and data output device for outputting the data alternately transferred by the first and second data transfer device. |