| abstract |
A method and novel DRAM cell design are described for making DRAM devices with more than a Gigabit memory cells. After forming the FETs and polycide word lines with a cap oxide and sidewall spacers, a thin diffusion protection oxide is deposited and openings are formed for contacts to the substrate. A conductively doped first polysilicon layer is deposited and polished back to the cap oxide. The first polysilicon remaining in the recesses between word lines is patterned to form first plug that are auto self-aligned (zero alignment error) to the word lines to achieve a very high density (Gigabit) memory. A planar first insulating layer with openings for bit lines is formed. Polycide bit lines are formed having a Si3N4 cap layer and sidewall spacers. Contact openings are selectively etched in the first insulating layer to first plugs and self-aligned to the bit lines. A doped second polysilicon layer is deposited and polished back to the Si3N4 cap layer, and the remaining polysilicon between bit lines is patterned to form auto self-aligned capacitor node-contacts to further increase memory cell density. A second insulating layer is deposited, in which DRAM capacitors are formed to complete the high density of memory for Gigabit DRAM devices. The auto self-aligned process eliminates critical photomask alignment and etching. |