| abstract |
Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid, conductive lining, such as, a hard metal, e.g., W, Mo, Os, Ir or alloys thereof. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating the hard metal to line the interconnection system and forming dielectric protective layers, e.g., a silane derived oxide bottommost protective layer, on the uppermost metallization level. |