http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6207501-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 1999-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_647b374219e9ff312de41a213946f024 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_daf3c41c8e78c2c710584d1ac3292c52 |
| publicationDate | 2001-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-6207501-B1 |
| titleOfInvention | Method of fabricating a flash memory |
| abstract | A method of fabricating a flash memory is disclosed: firstly, a P-type silicon substrate is divided into a PMOS area, an NMOS area, and a flash memory area. The first polysilicon layer and the first oxide layer are formed at the flash memory area. Thereafter, the second polysilicon layer, the second oxide layer, and a layer of TEOS are formed. The first photo resist is then formed to define the gate pattern of the flash cell array, and then a process of N + ion implantation is performed to form the source and drain of the flash cell array. After stripping the first photo resist, the second photo resist is formed to define the gate pattern at the NMOS area, and a process of N + ion implantation is performed to form the NLDD structure. After stripping the second photo resist, the first sidewall is formed, and then a process of N − ion implantation is performed to form the NMOS source/drain. The third photo resist is then formed to define the gate pattern at the PMOS area. A process of P − ion implantation is performed to form the PLDD structure, and then the third photo resist is stripped. The second sidewall is formed, and then the fourth photo resist is formed. A process of P + ion implantation is performed to form the source/drain structure at the PMOS area. Finally, the fourth photo resist is stripped. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006267134-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8258028-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005040474-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6472271-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6841824-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005093055-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7081381-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7679130-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6689653-B1 |
| priorityDate | 1998-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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