http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6171896-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76229 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate | 1997-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_27d5e02520f3050ff3402fd7bc1a17f6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c12c5b9338b2ab0a86bc203b2928e62b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7eb213879a3d808876e13769e95d55d7 |
| publicationDate | 2001-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-6171896-B1 |
| titleOfInvention | Method of forming shallow trench isolation by HDPCVD oxide |
| abstract | A method for forming planarized shallow trench isolation is described. A pad oxide layer is grown over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches are etched through the nitride and pad oxide layers into the semiconductor substrate wherein there are at least one first wide nitride region between two of the trenches and at least one second narrow nitride region between another two of the trenches. A high density plasma oxide layer is deposited over the nitride layer and within the isolation trenches wherein the high density plasma oxide layer fills the isolation trenches and wherein the high density plasma oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer. A photoresist mask is formed over the high density plasma oxide layer. The substrate is exposed to actinic light wherein a central portion of the first region is exposed. The high density plasma oxide layer is etched away where it has been exposed. The high density plasma oxide layer remaining is polished away whereby the substrate is planarized and fabrication of said integrated circuit device is completed. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10074721-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7364975-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10134603-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10403724-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6821865-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6667223-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004126986-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6734080-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6344383-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008020534-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6703287-B2 |
| priorityDate | 1997-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.