| abstract |
There is disclosed an integrated circuit comprising a test access port controller having a first mode of operation in which it is connectable to test logic to effect communication of serial test data and the control of an incoming clock signal, and a second mode of operation in which a data adaptor is connected to input and output pins via the test access port controller, the data adaptor being supplied with parallel data and control signals from on-chip functional circuitry and converting such parallel data and control signals into a sequence of serial bits including flow control bits. |