| abstract |
An efficient RF telemetry transmitter system includes a first stage and a second stage. The transmitter system sends power and data to an implant device using pulse-width modulation of a high fixed frequency clock signal, e.g., a 49 MHz clock signal, within the first stage in order to provide efficient generation of an RF output signal in the second stage. Digital logic gates and related circuitry, e.g., implemented in an application specific integrated circuit (ASIC), are used in the first stage to provide pulse-width modulation of the fixed frequency clock signal in order to optimally set the drive level of the output signal of the first stage, or inter-stage signal. ON/OFF keying, or other modulation scheme, further modulates the clock signal with data in the first stage. The second stage includes a Class-E amplifier circuit implemented with a single RF transistor, biased with a temperature-compensated offset voltage set just below the cut-off voltage of the transistor. An LC filter placed in the front end of the second stage filters out all but the fundamental frequency component of the inter-stage signal. The drive level of the inter-stage signal is selected to prevent both overdriving and underdriving of the Class-E amplifier. An adjustable or selectable collector voltage coupled to the single RF transistor allows the amplitude of the output signal to be set to an optimum power level for transmission to the implant device. |