| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
1997-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2000-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_804b153ecc5a2c80ed41b36602131833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_73ea192e1c746f038f4f2763dab09af2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_922e220d8b71b2f35158448031db1e70 |
| publicationDate |
2000-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6051863-A |
| titleOfInvention |
Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed |
| abstract |
A method is provided for fabricating a transistor gate conductor having opposed sidewall surfaces upon which dielectric spacers are formed such that the spacer profile substantially tapers toward the adjacent gate conductor sidewall surface as it approaches the base of the gate conductor. More particularly, formation of the sidewall spacers involves anisotropically etching a dielectric material deposited across a semiconductor topography in the presence of a passivant source to form a passivant upon portions of the dielectric material. The passivant primarily accumulates upon the upper portion of lateral surfaces of the dielectric material. An isotropic etch which occurs at the same rate in all directions is used to etch portions of the dielectric material not completely covered by the passivant. The resulting spacers have a varying thickness which decreases from top to bottom. Thus, when a silicide-forming metal is deposited, the metal accumulates at the peak of each spacer and is inhibited from being deposited upon the lower portions of the spacers, thereby preventing silicide bridging between the gate conductor and ensuing source/drain regions of the transistor. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014042550-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6500745-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7572719-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6368963-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6509221-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7994006-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8962429-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6232192-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6312999-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006118887-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6372591-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022216326-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6921725-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6362062-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7033954-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009075433-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6346449-B1 |
| priorityDate |
1997-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |