| abstract |
A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a substrate layer formed upon a substrate employed within a microelectronics fabrication. There is then formed upon the substrate layer a pair of patterned titanium nitride conductor layers upon which is formed a pair of aluminum containing conductor layers to provide a pair of patterned conductor stack layers. There is then formed over the patterned conductor stack layers a silicon oxide dielectric layer formed employing an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing tetra-ethyl-ortho-silicate (TEOS) as the silicon source material, where the silicon oxide dielectric layer defines at least in part a series of voids formed interposed between the patterned conductor stack layers. The substrate layer composition, the patterned conductor stack layer separation, the titanium nitride layer thickness, and at least one of the SACVD method parameters of deposition pressure or deposition temperature are selected such that the series of voids within the silicon oxide gap filling dielectric layer are interposed between the pair of patterned conductor stack layers. |