| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_02660742d97aafc1000d2a855884da59 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30134
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3861
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-261
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3844
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3853
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3838 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-26 |
| filingDate |
1997-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1999-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9dae029bbbd2191b4dd20ed7224c42eb |
| publicationDate |
1999-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-5918032-A |
| titleOfInvention |
Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions |
| abstract |
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6108768-A |
| priorityDate |
1989-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |