| abstract |
Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs. A corner tile is also provided that permits interconnection between horizontal and vertical tiles. The tiles are modular in nature so the number of tiles provided within an array and their placement are determined based on the array's particular need for routing resources, e.g., an array can have one, two or more tiles associated with a row or column of CLBs in areas of the chip where congestion is typically encountered. Each tile of the present invention can also include a plurality of switch matrices, buffers, or other active gates to facilitate signal routing. |