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filingDate 1997-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1998-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17ab5cf704df7b67f60b9b4ceb2c01a7
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publicationDate 1998-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-5828111-A
titleOfInvention Increase resistance of a polysilicon load resistor, in an SRAM cell
abstract A method for fabricating polysilicon load resistors, with increased resistance values, for use in SRAM cells, has been developed. An underlying, raised grid topography is used to allow the overlying polysilicon load resistor to traverse the severe topography, resulting in an increase in resistor length, while still maintaining the allotted design space, overlying a MOSFET device. The formation of back to back diodes in the polysilicon load resistor also results in an increase in resistance. The back to back diodes are created via N type, ion implantation into only flat regions of an intrinsic, or P type doped, polysilicon load resistor, regions in which the polysilicon load resistor overlaid the flat regions of the underlying raised grid topography, leaving regions of the polysilicon load resistor, located on the sides of the underlying raised grid topography, P type.
priorityDate 1996-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 27.