| abstract |
An electronic system, such as a computer system, in which access to configuration registers used by a memory controller, is selectively enabled. The disclosed system includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, a bus bridge circuit, and configuration registers. The microprocessor unit is connected to external dynamic random access memory (DRAM). The memory controller circuit is operable to perform an operation utilizing current information in one or more of the configuration registers. The bus bridge circuit includes a request logic circuit for supplying a request output signaling an impending access to one or more of the configuration registers. The memory controller circuit includes a reply logic circuit for supplying a reply output back to the request logic circuit after the operation utilizing current configuration register information is completed. The request logic includes an enable circuit responsive to the reply output to then enable the impending access to the configuration registers. The electronic system may also include one or more additional integrated circuit devices, such as may include a direct memory access (DMA) circuit and a bus bridge interface circuit for bidirectional communication with the microprocessor unit. The microprocessor unit may also include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for determining memory bank size and memory address type. |