http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5686330-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e08fd85d97265d6c31ab40f372843d81 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66416 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7722 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-335 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-772 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-80 |
| filingDate | 1996-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1997-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b121bdd0aa670eadabf23625322c1be7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f6756d0cc6b6a8022aa8c10864312ee1 |
| publicationDate | 1997-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-5686330-A |
| titleOfInvention | Method of making a self-aligned static induction transistor |
| abstract | A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-aligned relatively deep trench in accordance with the present invention is formed over the gate regions. This is achieved by forming an oxide layer, and forming a polysilicon layer on the oxide layer. A second oxide layer is formed on the polysilicon layer which is then masked by a self-aligning mask. Trenches are etched into the source and gate regions using the self-aligning mask and gate regions are formed at the bottom of the trenches. The transistors are then processed to completion by forming gate, source and drain regions. This portion of the method comprises the steps of forming maskless self-aligned gate metallization, forming maskless self-aligned contacts to the gate metallization and filling the trench, forming source metallization, and forming a drain contact on the substrate. The method employs a single minimum geometry trench mask. The key features of the transistors are defined by the trench mask and related processing parameters. Because of the self-alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded gate junction. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007194364-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7855413-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8716785-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2033224-A2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2033224-A4 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101535222-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009261420-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2002155655-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003042555-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6800918-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8889539-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8519410-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012217578-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7230298-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7009228-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011049532-A1 |
| priorityDate | 1995-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.