| abstract |
A process for fabricating a deep submicron MOSFET device has been developed, featuring a local threshold voltage adjust region in a semiconductor substrate, with the threshold voltage adjust region self aligned to an overlying polysilicon gate structure. The process consists of forming a narrow hole opening in a dielectric layer, followed by an ion implantation procedure used to place the threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. A polysilicon deposition, followed by a chemical mechanical polishing procedure, results in the creation of a narrow polysilicon gate structure, in the narrow hole opening, self aligned to the threshold voltage adjust region. |