http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5554568-A

Outgoing Links

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filingDate 1994-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1996-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2fc7b1e19034478f18f19f4e9397ae2c
publicationDate 1996-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-5554568-A
titleOfInvention Polysilicon trench and buried polysilicon wall device structures
abstract This invention describes a device structure and a method of forming the device structure using trenches with sidewalls formed in the substrate of an integrated circuit. A highly doped polysilicon layer is formed on the walls of the trench or the trench is filled with highly doped polysilicon to form the source and drain of a field effect transistor in an integrated circuit. The invention provides reduced source and drain resistance. The capacitances between the gate and source and the gate and drain are reduced as well.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6100172-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6008079-A
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priorityDate 1994-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 30.