http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5498553-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S148-126 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1087 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0927 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0638 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 1993-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1996-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11d4168cbd11f5b02d6d18bb81324c78 |
| publicationDate | 1996-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-5498553-A |
| titleOfInvention | Method of making a metal gate high voltage integrated circuit |
| abstract | A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided. The method comprises forming a first masking layer on the surface of the substrate, providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first implant regions in the well on either side of a first central region in the well and in a set of second implant regions adjacent to the well on either side of a second central region adjacent to the well, formation of insulating structures over the first and second regions, forming gate oxide layers above the first and second central regions, forming a second masking layer on the surface of the substrate, providing openings in the masking layer and implanting dopant ions of a second polarity into the surface of the substrate in a set of second implant regions in the well on either side of a first central region in the well and in a set of fourth implant regions adjacent to the well on either side of a second central region adjacent to the well, and formation of conductive gate structures over the gate oxide layers. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5693505-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105321944-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5946564-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6215151-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105321944-A |
| priorityDate | 1993-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.