| abstract |
A DDD-type cardiac pacemaker having a microprocessor-based controller is programmed to automatically determine and utilize and optimize A-V delay for the patient in whom the device is implanted. The microprocessor-based controller periodically changes the A-V delay and then computes heart rate variability over an insuing predetermined period. The particular A-V delay value associated with the minimum heart rate variability index is determined to be the optimum. Heart rate variability may be determined by performing a power spectrum analysis on cyclic variations in R-R intervals, preferably using a FFT signal processing chip, or by a time domain analysis based upon the standard deviation of R-R intervals during a prescribed period of time and a calculated value of respiratory sinus arrhythmia. The apparatus is also operative to optimize the A-V delay interval following a change in the pacing mode of the DDD-type pacemaker. |