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filingDate 1992-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1994-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c82ef0b38f87ead6654297a204b73105
publicationDate 1994-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-5281544-A
titleOfInvention Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors
abstract A sidewall construction is utilized in the method of manufacture of semiconductor devices comprising planar type bipolar transistors wherein the width of the sidewall construction can be accuracy controlled which, in turn, controls accuracy the channel length of the base of the planar type bipolar transistors. This technique provides ways of preventing short circuiting between the formed transistor collector and emitter regions of the planar type bipolar transistors. The sidewall construction can also be employed in fabrication combination planar type bipolar/MIS type transistors resulting in higher density of these structures over the prior art laterally positioned structures.
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priorityDate 1990-07-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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