| abstract |
This chip-to-test (1) has a passivation layer and an overlayer at test points (4). The system comprises a vacuum chamber (8), means (2) for mounting and connecting the chip-to-test (1), a pulsed light source means (9) operable to scan the chip-to-test (1) for inducing photoelectron (15) emission therefrom, means (14) for exercising the circuits of the chip-to-test (1), means (18) for detecting the photoelectrons (15), having a detection threshold and delivering a sequence of signals representative of voltages at the currently scanned test point (4') or points as a function of the scanned point or scanning time, means (23) for flooding the chip-to-test (1) with electrons of energy lower than the detection threshold, means (21) for analyzing said sequence of signlas and means (22) for deriving therefrom a capacitive voltage contrast. The material of the overlayer has a work function lower than the photon energy and can be BeO, MgO, CaO, TiO2, more preferably SrO, Cs2O, BaO or a mixture thereof. This system facilitates testing of a chip-to-test whose passivation layer has a work function above the photon energy, and prevents charging-up of the passivation layer. |