http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5011785-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7b94d2715cda37c1f23e48f9f4f23422 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-978 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66901 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1066 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66924 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-335 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-337 |
| filingDate | 1990-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1991-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_351a354887fcdf7830588b0c26e080c2 |
| publicationDate | 1991-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-5011785-A |
| titleOfInvention | Insulator assisted self-aligned gate junction |
| abstract | A high transconductance, low capacitance, low leakage compound semiconduc junction field effect transistor (JFET) enhances the low leakage current while having the advantages of a self-aligned JFET including low capacitance and low source-drain resistance. The diffused junction of the JFET is totally covered during the process of manufacture. An n channel on a substrate has a layer of photoresist placed over it and exposed to leave a predefined pattern of photoresist. The patterned photoresist is used as a mask so that part of the n-channel layer is etched down to a desired depth leaving a wedge-shaped region. A layer of insulator, such as silicon dioxide, is deposited over the entire substrate and sides of the w edge-shaped region in insulator regions. Next, the photoresist is then removed. A p + diffusion or implant is performed in the wedge-shaped region to create a p + n-junction system which is the gate region of the JFET. The p + n junction system sides are covered the insulator regions of silicon dioxide unlike the opened-junction of the conventional self-aligned gate JFET. Next, the gate patterned metal is deposited on top of the p + n junction system and partially on the silicon dioxide insulator regions. Using the patterned gate metal as a mask, the silicon dioxide layer is removed. Source and drain metals are then self-aligned evaporated. The JFET has potential use in microwave, millimeter-wave and optical electronic circuits. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6051856-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010213556-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007007605-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8022459-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5116774-A |
| priorityDate | 1990-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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