| abstract |
In a computer network having a system bus, a system processor connected to the system bus, and a plurality of local processors each connected to a respective local bus each having a plurality of interface cards attached thereto, each interface card includes an identification ROM. Each interface card responds to an initial reset signal enabling that interface card to respond to the same initial address. Each local processor outputs that initial address. The closest interface card of each local bus responds by transmitting information from its identification ROM to the requesting local processor, which then assigns an address to the closest interface card, which then automatically sets circuitry that enables the next closest interface card to respond to the initial address. The procedure is repeated to assign unique addresses to all of the interface cards. |