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filingDate 1986-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1987-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa46d822e4fb3aecc44d1ca1e8cca616
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publicationDate 1987-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-4659428-A
titleOfInvention Method of manufacturing a semiconductor device and semiconductor device manufactured by means of the method
abstract An improved method of manufacturing a semiconductor device having a narrow groove or slot is provided. There are formed on a substrate a heavily n-doped first silicon layer, an oxidation-preventing layer such as silicon nitride, and a weakly doped or undoped second silicon layer. By means of a single masking step, a part of the second silicon layer is removed, and the remaining part is partially oxidized. The exposed portion of the oxidation-preventing layer is removed without a further masking step by using the oxidized remaining parts of the second silicon layer. Subsequently, the oxide on the second silicon layer is removed. By thermal oxidation, a thin oxide layer is formed on the second silicon layer and an about ten times thicker oxide layer is formed on the first silicon layer. After the exposed oxidation-preventing layer has been etched away, the oxide on the second silicon layer is etched away entirely, and the oxide on the first silicon layer is etched away only superficially. After this, a groove is etched at the removed portions of the exposed oxidation-preventing layer while simultaneously removing the remaining parts of the second silicon layer.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010219409-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5067002-A
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018090319-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8039833-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7767999-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5397723-A
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Total number of triples: 54.