http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4573256-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S148-01 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7325 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-732 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-73 |
| filingDate | 1983-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1986-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fbe3829f2b91c0d3eee5d0a4f08f0f92 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21baed2f80bff96ef62c985832d6db33 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5fb5c9575b9d4404f4662b050634cccd |
| publicationDate | 1986-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-4573256-A |
| titleOfInvention | Method for making a high performance transistor integrated circuit |
| abstract | A process for making high performance NPN bipolar transistors functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body. The transistor includes an N+ subcollector, and N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region extending from the major surface and adjacent to the emitter region. The extrinsic base completely surrounds the emitter region. A mask is formed above the major surface having openings only above major portions of the extrinsic base regions. A P+ region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made and the elements are connected in a current switch logic circuit. The use of high conductivity P+ region in the extrinsic base region closely adjacent to the emitter reduces the extrinsic base resistance. Independent doping in the extrinsic base through the mask openings allows independent control of the intrinsic and extrinsic base resistances. These changes increase the performance of bipolar transistor integrated circuits for current switch logic applications. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014308792-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9281375-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5298440-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5528066-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4967254-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4819049-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5063167-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5118634-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6140194-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4721685-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5716859-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4669179-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011106187-A1 |
| priorityDate | 1983-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 50.