| abstract |
In a circuit arrangement having a plurality of field effect transistors which are connected in series and operate simultaneously, the circuit arrangement is free from restriction of an operating frequency and it is not necessary to provide an individual power source for gate biasing, so that the construction of the circuit arrangement is simplified and the cost is reduced. n A gate drive pulse is applied to the gate of the field effect transistor (Q2) on a common potential point side. A parallel connection circuit having a first resistor (R3) and a first capacitor (C3) is coupled between the gate of the other field effect transistor (Q1) and the common potential point side. A parallel connection circuit having a second resistor (R4) and a second capacitor (C4) is coupled between the first electrode (e.g. drain) and the gate of the other field effect transistor. A capacitance of the first capacitor is larger than that of the second capacitor, so that the other field effect transistor is sufficiently shifted to a conductive state when the gate drive pulse is applied to the field effect transistor on the common potential side. |