http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4377853-A

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filingDate 1980-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1983-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_afc3aa3b4b36706eed444b55d5a5611b
publicationDate 1983-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-4377853-A
titleOfInvention Peripheral controller with segmented memory buffer for interfacing 80 column card reader with host computer
abstract In a peripheral controller for a card reader in an I/O subsystem, there is provided a buffer memory for storing, in separate dedicated portions, raw data from the card reader and translated data processed by a translator circuit means. Multiplexer means provide for the receipt and storage in memory of raw card data and/or receipt and storage of translated data which has been processed into selected formats for later transmittal to a main host system. A shift register translator, operating under commands from said host system, operates to take raw card data from said buffer-memory, and to format it into a desired word structure for re-storage in said buffer memory. The multiplexer means and a data register can then select the formatted data for transmittal to the main host system.
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Total number of triples: 34.