http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4268328-A

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filingDate 1980-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1981-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa1e0410b46389d2af66de04ad46fe93
publicationDate 1981-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-4268328-A
titleOfInvention Stripped nitride MOS/MNOS process
abstract A method for fabricating MOS and MNOS transistors on a common substrate which strips the silicon nitride required for MNOS operation away from areas where it is not required. The removal of the nitride from the MOS gate eliminates cumulative threshold instability and allows separate optimization of both MOS and MNOS structures in a single process. Removal of nitride from other areas such as the contact regions prevents undercut structures of nitride dielectric from being formed during contact hole fabrication and thus minimizes reliability problems and yield limitations. Further an improved MNOS structure is produced which has strips of nitride in the gate region spaced apart from the diffused regions, thereby minimizing diode breakdown and long term threshold instability.
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Total number of triples: 28.