| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_79b5f9d76648dfc226a261cfb970de9c |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N1-3875
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N1-40 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N1-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N1-387 |
| filingDate |
1977-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1979-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0795c726ce9c14468d4a0ca77a3d2cfb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1fb3b9980a936368938669437978905d |
| publicationDate |
1979-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-4133007-A |
| titleOfInvention |
Video data detect circuits for video hard copy controller |
| abstract |
Video data detect circuits are provided for a video hard copy controller of the type that converts and formats a video signal into a digital signal for application to a hard copy generating device. The video signal includes a video data component and a synchronization component including horizontal synchronization (HS) periods. The video hard copy controller includes means for generating sample clock pulses at a frequency proportional to the HS periods. The video data detect circuits comprise first means for generating a predetermined video threshold reference signal; second means coupled to the first means and responsive to the video signal and to the predetermined reference signal for generating a binary signal at one state for so long as the voltage level of the video signal exceeds that of the predetermined reference signal and at another state for so long as the voltage level of the video signal is less than that of the predetermined reference signal. Third means is coupled to the second means and is responsive to the sample clock pulses and to the binary signal for coherently sampling the state of the binary signal at a predetermined transition of each sample clock pulse in order to generate the digital signal. |
| isCitedBy |
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| priorityDate |
1977-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |