| abstract |
In a transistor packaging having an input, an output and a common lead, the common lead includes a pair of terminal strip portions disposed on opposite sides of the transistor die. An array of generally parallel common connector wires interconnect both of the common lead terminal strip portions and one of the base or emitter electrode structures on the transistor die. The other one of the emitter or base electrode structures is connected to the input lead via the intermediary of an array of wires interdigitated with the array of common connector wires. In this manner, the common lead inductance of the transistor package is reduced resulting in improved gain and/or r.f. stability of the transistor. |