| abstract |
A single input channel cascade FFT processor includes a plurality of substantially identical arithmetic units connected by a delay and switching arrangement for selectively delaying subsets of input data samples and intermediate results. By reordering an input sequence and thus selectively delaying, all components are operated at full capacity at all times, while a reduced amount of storage (delay) is required. Alternate embodiments provide for multiplexing a plurality of input data channels and multiplexing arithmetic units among a plurality of stages. |