http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-3603771-A

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classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-394
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-535
filingDate 1969-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1971-09-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2af72fc927f704ed39a28902afd3e723
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8cdc19bdc62bf646d892280a21686cbe
publicationDate 1971-09-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-3603771-A
titleOfInvention Input/output signal point assignment
abstract Active components, such as logic gates or flip-flops, formed in a semiconductor substrate are interconnected to input/output bonding pads and other active components in a circuit array in four separate operations. First, after arranging the active components in rows, signal points of all components in one row are interconnected by considering the longest interconnection and proceeding to the shortest. Next, component signal points between rows are interconnected again by considering the longest interconnecting path and proceeding to the shortest path. Third, input/output component signal points are assigned to input/output conductive pads. Finally, interconnecting paths are completed between the input/output component signal points and an assigned pad in a numbered order. Each operation uses a distinct algorithm to complete the necessary steps.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4093990-A
priorityDate 1969-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 48.