| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cdd6ba86faf29d8538432c5419503fbf |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5061
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30029 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0679
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1075
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-061
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0655 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F30-39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-50 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 |
| filingDate |
2022-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2eecfc60831fd81a1c71db331a337d1c |
| publicationDate |
2023-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2023013962-A1 |
| titleOfInvention |
Apparatus and architecture of non-volatile memory module in parallel configuration |
| abstract |
A non-volatile memory module in parallel architecture is described. It includes memory function and data storage function in a single module. It enables host system to use memory bus to access storage devices and to use the same memory command protocol for storage device access. The parallel architecture enables contents in memory devices and storage devices to be exchanged freely on module under the control of host memory controller to boost performance of computer and to retain data even if power to computer is shut off. The configuration of non-volatile memory module can be partitioned or expanded into multiple independent channels on module seamlessly with or without ECC supports. |
| priorityDate |
2017-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |