| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cd75bebe3b375c0b208631e4bb176ed0 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0948
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0727 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0948
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0948
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2020-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_902352a934244ce77f2d4411606f9109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e7fa0209f1c6e2b5f5b2e373945be2e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8874f944b75f010d156ec88f87977621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_87f2972720af3fa14bfdc306a71b2849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dee6010127c151275fd2066ee5631334 |
| publicationDate |
2022-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2022285507-A1 |
| titleOfInvention |
Transistor, ternary inverter including same, and transistor manufacturing method |
| abstract |
A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions. |
| priorityDate |
2019-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |