Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4991 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0665 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
filingDate |
2020-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cdb64bfc290946e2ef335e7d5a346cc2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98c97f8ef4800f36cd432009aee57f30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e4ba388609e912252e1241aef24ed35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eb1b4fac313511e6db4d29727f2a2727 |
publicationDate |
2021-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2021391423-A1 |
titleOfInvention |
Semiconductor Device with Facet S/D Feature and Methods of Forming the Same |
abstract |
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises alternately forming first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction substantially perpendicular to a top surface of the substrate; forming a dummy gate structure over the first and second semiconductor layers; forming a source/drain (S/D) trench along a sidewall of the dummy gate structure; forming inner spacers between edge portions of the first semiconductor layers, wherein the inner spacers are bended towards the second semiconductor layers; and epitaxially growing a S/D feature in the S/D trench, wherein the S/D feature contacts the first semiconductor layers and includes facets forming a recession away from the inner spacers. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022238650-A1 |
priorityDate |
2020-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |