| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6caea61bfde8a45e01a8deabff80d97 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78391
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11597
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1159
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11587
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40111 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11587
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11597
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1159 |
| filingDate |
2020-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2299a025a2aed6b0c65d5bff46b62bc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2442f78fc9835ecdbe086c06c1676c8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b93389fb44e0db9a4291ffdd1de29952
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_38186f603b236b5cf68056e00c9b3729
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_309722f584db4e6f65a532bd17c76673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c02572981ba2bfb0272532e9bee3d429 |
| publicationDate |
2021-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2021358952-A1 |
| titleOfInvention |
Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same |
| abstract |
A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023065891-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11545506-B2 |
| priorityDate |
2020-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |