| abstract |
The present disclosure provides a shift register unit, including an input sub-circuitry, a pull-up node control sub-circuitry, a pull-down node control sub-circuitry, a gate driving output sub-circuitry and a carry signal output sub-circuitry. The input sub-circuitry is connected to an input end, a second clock signal input end and a pull-up node. The pull-up node control sub-circuitry is connected to the pull-up node, a pull-down node, a first clock signal input end and a first voltage input end. The pull-down node control sub-circuitry is connected to the pull-down node, the pull-up node, the first clock signal input end, the first voltage input end and a second voltage input end. |