http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021327767-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8fbf590463d3518a746d90a6a2c1c34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e829b93e1bdf87272f2aaf3baaaa0f4 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2021-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d91039b7af740d61d87657bafbb2023d |
| publicationDate | 2021-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2021327767-A1 |
| titleOfInvention | Semiconductor structure and method for forming same |
| abstract | A semiconductor structure and a method for forming same are provided. One form of the forming method includes: providing a base, the base including: a substrate and a channel stack on the substrate, the channel stack including a first channel layer and a second channel layer located on the first channel layer, the first channel layer and the second channel layer being made of different materials, and a first region and a second region, where the channel stack is located in the first region and the second region; forming an interlayer dielectric layer on the substrate exposed from the channel stack, where a gate opening from which the channel stack is exposed is formed in the interlayer dielectric layer; removing the second channel layer of the first region in the gate opening; removing the first channel layer of the second region in the gate opening; and forming a gate structure surrounding a remainder of the first channel layer and the second channel layer. In some implementations of the present disclosure, channel regions of transistors in the first region and the second region are made of different materials to meet performance requirements of different transistors, thereby optimizing electrical performance of the semiconductor structure. |
| priorityDate | 2020-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.