Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0665 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
filingDate |
2020-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_348326ab514983573664efae62e36689 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_13d025559edc2387314189acef1872b3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d05f1f86d9fa7250567755f12c7d0d53 |
publicationDate |
2021-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2021305420-A1 |
titleOfInvention |
Enhanced bottom dielectric isolation in gate-all-around devices |
abstract |
A gate-all-around (GAA) semiconductor device structure and method for forming the same. The GAA structure includes a nanosheet stack disposed over a patterned portion of a substrate, and an encapsulation structure surrounding the patterned portion of the substrate underlying the nanosheet stack. The method for forming the GAA structure includes forming a liner over and in contact with a nanosheet fin, a sacrificial layer disposed below the nanosheet fin, and a patterned portion of a substrate underlying the nanosheet fin. At least one portion of the liner is etched down to the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the nanosheet fin and the patterned portion of the substrate. An insulting layer is formed within the cavity, where the patterned portion of the substrate within one or more gate regions is encapsulated by the insulting layer and the liner. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023168570-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11710742-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022005931-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022165733-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11430789-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11456292-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023064751-A1 |
priorityDate |
2020-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |