| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-315 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0387
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0335
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10882
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-373
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76837
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate |
2020-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_880cb08eb3c6f1e4b09198cdfa3178d5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6d2ccfd83c4b1a3fa3db7295906e1ba9 |
| publicationDate |
2021-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2021265359-A1 |
| titleOfInvention |
Integrated Circuitry, DRAM Circuitry, Method Used In Forming Integrated Circuitry, And Method Used In Forming Memory Circuitry |
| abstract |
A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias, Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness. A plurality of electronic components is formed above the fourth insulating material and that individually are directly electrically coupled to individual of the conductive vias through the fourth and second insulating materials. Other embodiments, including structure, are disclosed. |
| priorityDate |
2020-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |