http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021263796-A1

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0411
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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-42
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-021
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-52
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10
filingDate 2021-04-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_73aa9042cad9bec6b7d14a4e2a24fe91
publicationDate 2021-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021263796-A1
titleOfInvention Semiconductor device having error correction code (ecc) circuit
abstract An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.
priorityDate 2015-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
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Total number of triples: 23.